1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to the manufacture of transistors having strained channel regions by using stress-inducing sources, such as globally strained silicon substrates and the like, in order to enhance charge carrier mobility in the channel region of a MOS transistor.
2. Description of the Related Art
Generally, a plurality of process technologies are currently practiced to fabricate integrated circuits, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is presently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode located in close proximity to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region is a dominant factor determining the performance of MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is an important design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith, such as reduced controllability of the channel, also referred to as short channel effects, and the like, that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For instance, the thickness of the gate insulation layer, typically an oxide-based dielectric, has to be reduced with reducing the gate length, wherein a reduced thickness of the gate dielectric may result in increased leakage currents, thereby posing limitations for oxide-based gate insulation layers at approximately 1-2 nm. Thus, the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques, for example, for compensating for short channel effects with oxide-based gate dielectric scaling being pushed to the limits with respect to tolerable leakage currents. It has, therefore, been proposed to also enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to technology nodes using reduced gate lengths while avoiding or at least postponing many of the problems encountered with the process adaptations associated with device scaling.
One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance, by creating tensile or compressive stress in the vicinity of the channel region so as to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating uniaxial tensile strain in the channel region along the channel length direction for a standard crystallographic orientation increases the mobility of electrons, which in turn may directly translate into a corresponding increase in the conductivity. On the other hand, uniaxial compressive strain in the channel region for the same configuration as above may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach for further device generations, since, for example, strained silicon may be considered as a “new” type of semi-conductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
In some approaches, external stress created by, for instance, permanent overlaying layers, spacer elements and the like is used in an attempt to create a desired strain within the channel region. Although a promising approach, the process of creating the strain in the channel region by applying a specified external stress may depend on the efficiency of the stress transfer mechanism for the external stress provided, for instance, by contact layers, spacers and the like into the channel region to create the desired strain therein. Thus, for different transistor types, differently stressed overlayers have to be provided, which may result in a plurality of additional process steps, wherein, in particular, any additional lithography steps may significantly contribute to the overall production costs. Moreover, the amount of stress-inducing material and, in particular, the intrinsic stress thereof may not be arbitrarily increased without requiring significant design alterations.
In other approaches, a strain-inducing semiconductor alloy may be provided within drain and source regions, which may exert a specified type of stress on the channel region to thereby induce a desired type of strain therein. For example, a silicon/germanium alloy may frequently be used for this purpose in order to obtain a compressive stress component in the adjacent channel region of, for instance, P-channel transistors in order to increase mobility of holes in the corresponding P-channel. In sophisticated applications, two or more of the above-specified strain-inducing mechanisms may be combined so as to further enhance the overall strain obtained in the corresponding channel regions. However, these strain-inducing mechanisms may be considered as “local” mechanisms, since the strain may be induced in and above the corresponding active region for the transistor element under consideration, wherein the finally obtained strain component in the channel region may significantly depend on the overall device dimensions. That is, typically, these local strain-inducing mechanisms may rely on the stress transfer capabilities via other device components, such as gate electrodes, spacer elements formed on sidewalls of the gate electrodes, the lateral dimensions of the drain and source regions and the like. Consequently, the magnitude of the strain in the channel region may significantly depend on the technology under consideration, since, typically, reduced device dimensions may result in an over-proportional reduction of the corresponding strain-inducing mechanism. For example, creating strain by a dielectric overlayer, such as a contact etch stop layer, may frequently be used, wherein, however, the amount of internal stress of the corresponding dielectric material may be restricted by deposition-related constraints while at the same time, upon reducing device dimensions, for instance the spacing between two neighboring transistor elements, may require a significant reduction of the layer thickness, which may thus result in a reduction of the finally obtained strain component. For these reasons, typically, the magnitude of the strain in the channel region provided by the local strain-inducing mechanisms may be several hundred MPa, while a further increase of this value may be difficult to be achieved upon further device scaling.
For this reason, attention is again increasingly drawn to other mechanisms in which a moderately high degree of strain may be created in a global manner, i.e., on a wafer level, so that the corresponding active regions of the transistor elements may be formed in a globally strained semiconductor material, thereby providing a “direct” strain component in the corresponding channel regions. For instance, as one of the earliest strain techniques, a silicon material may be epitaxially grown on an appropriately designed “buffer layer” in order to obtain a strained silicon layer. For example, a silicon/germanium buffer layer which may be provided with its substantially natural lattice constant may be used for forming thereon a strained silicon layer, which may have a moderately high tensile biaxial strain of 1 GPa or higher, depending on the lattice mismatch between the buffer layer and the strained silicon layer. For example, a substantially relaxed silicon/germanium layer having a fraction of approximately 20 atomic percent germanium may result in a tensile biaxial strain of a corresponding epitaxially grown silicon material of 1.3 GPa, which is significantly higher compared to the strain levels obtained by the local strain-inducing mechanisms described above. The global biaxial strain in the silicon results in an increase of the degree of degeneration of the conduction band, thereby creating two sets of sub-valleys with different effective electron masses. An appropriate repopulation of the theses energy states thus leads to a higher electron mobility and hence a higher drive current of N-channel transistors.
The creation of a global strained silicon layer may also be efficiently accomplished on the basis of a silicon-on-insulator (SOI) architecture by sophisticated wafer bonding techniques. That is, a strained silicon layer may be formed on the basis of an appropriately designed buffer layer, as explained above, and the corresponding silicon layer may be bonded to a carrier wafer having formed thereon a silicon dioxide layer. After the bonding of the strained silicon layer to the carrier wafer, the strained semiconductor layer may be cleaved, for instance, by incorporating an appropriate species, such as hydrogen, helium and the like, wherein the previously generated strain may be substantially maintained due to the adhesion of the strained silicon material on the material of the carrier wafer. Consequently, a globally strained silicon layer may also be provided in applications in which SOI architecture may be required, at least for performance driven transistor elements.
Providing a globally strained silicon layer may be considered as a very promising approach for forming highly strained transistor elements, for instance, on the basis of an SOI architecture. A further increase of performance of complex CMOS devices may, however, also demand an appropriate strain engineering for P-channel transistors, for which the biaxial tensile strain of the globally applied silicon layer may result in a performance degradation. In this case, the difference in charge carrier mobility between N-channel transistors and P-channel transistors may be even further increased, thereby contributing to a further increased imbalance of performance behavior in complex CMOS devices, thereby rendering this approach less attractive for sophisticated applications. It has been observed, however, that a further increase of the global tensile strain level in strained SOI substrates, which may be achieved by using a higher germanium concentration in the silicon/germanium buffer layer, the hole mobility may exhibit a slight increase. These high strain levels, however, are difficult to achieve due to a significantly increased probability of creating dislocations, which may result in a relaxation mechanism of the strain above a certain critical thickness of the semiconductor layer. An increased level of dislocations, however, may result in a reduction of overall transistor performance, thereby reducing or even offsetting the advantages in N-channel transistors obtained by providing a globally strained silicon layer. On the other hand, it is very difficult to provide a globally compressively strained semiconductor layer, for instance, on the basis of a silicon/carbon buffer layer, since appropriate deposition techniques for growing a silicon/carbon alloy are very difficult to control on the basis of volume production regimes.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.